In computer systems signal lines such as data and address lines are typically present which must be driven by driver devices. For example, in conventional integrated circuit (IC) chips, 16 or 32 bit address and data buses are present, and in some advanced microprocessors, data bus widths are sometimes 128 and even 256 bits. These buses are inherently capacitive, the capacitance of which must be overcome by the driver device driving the signal onto these lines. Because capacitance is additive in parallel, as the bus width increases, so does the capacitance.
The capacitance of these signal lines also increases as the length of the lines increases. As IC chips increase in size, then, the problem of designing driver devices for these signal lines becomes more demanding, especially when all of the lines need to be driven simultaneously. Typically, the capacitance of these signal lines is on the order of several picofarads.
FIG. 1 shows a conventional driver device for driving capacitive signal lines. The inputs IN and IN-complement are output by a complementary metal-oxide semiconductor (CMOS) device (not shown). The pair of inverters on each complementary input build up the drive capability of the driver and drive the bus output lines OUT and OUT-complement, both of which have an inherent capacitance C.sub.BUS. The inverters are typical CMOS inverters comprising a PMOS pull-up transistor and an NMOS pull-down transistor.
When a signal bus is driven in the conventional manner as shown in FIG. 1, the OUT and OUT-complement bus lines experience a voltage swing which represents the change in voltage on a bus line during a transition when it is driven from a high to low voltage. The voltage swing on these bus lines is equal to the external voltage supply (e.g., 3.3 volts). The charge required to be built up by the CMOS inverters of FIG. 1 to effectively drive the bus lines OUT and OUT-complement is equal to this voltage swing multiplied by the capacitance of the bus (C.sub.BUS). Accordingly, the required charge increases with both increased supply voltage and increased bus capacitance.
Typically, these bus lines need to be driven in a very short time frame, on the order of one or two nanoseconds, and thus the current that must be provided by the CMOS driver device increases with decreased driving times. Merely increasing the voltage supply of the device driver is not an acceptable solution, however, because the increased voltage results in a larger voltage swing which increases the charge necessary to drive the bus, and, hence the input power requirements. Moreover, an increase in noise is typically an undesirable by-product of an increased voltage supply due to the increased transient currents experienced during voltage transitions.
One known solution of the capacitive bus driving problem is shown in an article entitled "Sub-1-V Swing Internal Bus Architecture for Future Low-Power ULSI's", IEEE Journal of Solid State Circuits, Vol. 28, April 1993. The disclosed solution relates to a technique for reducing the voltage swing on a capacitive bus to reduce input power requirements. Using on-chip regulators, two internal voltages are generated, both of which reside at levels between ground and the supply voltage on the bus to be driven. The differential between these two internally generated voltages is about one-half volt. A conventional CMOS inverter is operated between these voltages, rather than between the supply voltage and ground, as shown in the prior art driver device of FIG. 1, to reduce the voltage swing present on the bus to be driven. Hence, the power requirements are also reduced.
It is an object of the present invention, then, to provide a driver device for driving signals such as the address and data lines of a capacitive bus, which does not require the internal generation and regulation of additional voltage levels, but which reduces the power consumption required for operating the driver and minimizes noise due to transient currents produced during its operation.